Grant: $705,507 - National Science Foundation - Jul. 27, 2009
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Award Description: Power dissipation is widely recognized as the key bottleneck in electronic design and the development of energy efficient solutions is critical to the survival of the semiconductor industry. Solutions to the power conundrum must come from within CMOS technology through enhanced archi-tectures, circuits, and devices. We target â€œnear-threshold computingâ€? (NTC), where devices operate at or near their threshold voltage to obtain 10X or higher energy efficiency improvements. We will develop a synergistic approach combining methods from algorithm and architecture levels to the circuit and technology levels,
Project Description: To evaluate the existing error correction methodologies for memories in scaled technologies. Both hard errors and soft errors are considered.
Jobs Summary: Not applicable at this time (Total jobs reported: 0)
Project Status: Not Started
This award's data was last updated on Jul. 27, 2009. Help expand these official descriptions using the wiki below.