Grant: $499,789 - National Science Foundation - Aug. 31, 2009
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Award Description: This Small Business Technology Transfer (STTR) Phase II project will develop and apply a principled design methodology to confront the serious problems associated with deep sub-micron, system-on-chip (SoC) integrated-circuit designs. The support provided by this grant will establish the foundation for advanced SoC design services that will be particularly valuable to companies wishing to develop complex, proprietary, low-power integrated circuits. Current and future integrated circuit designs are topping the billion-transistor mark. With non-recurring engineering costs of ambitious SoCs nearing $65M, design and global verification costs are rapidly escalating and quickly becoming prohibitive for all but the highest volume products. A unique design tool will be developed and tested through its use in two challenging SoC designs. Our plan for this novel design tool will be to apply a mathematically sound approach to the globally-asynchronous, locally-synchronous methodology in order to produce large, delay-insensitive, hazard-free network-on-chip (NoC) designs. Our goal for this tool is to reduce traditional design cycles by eliminating most of the global verification effort while improving the robustness of the design. New results in predicting the behavior of deep sub-micron arbiter circuits are essential to this work and will also be reported. Achievement of our goal for this design tool has the triple advantage of reducing design costs, time-to-market and power consumption. More broadly this can: 1) significantly increase the productivity of integrated circuit design engineers, 2) reduce power consumption of electronic control, communication and computational systems and 3) increase our competitiveness against off-shire SoC designers particularly with respect to low-volume products. Thus, successful completion of this project is important to the future of the national electronics marketplace because without a major reduction in the time spent on global verification the benefits of higher levels of integration, including reductions in time-to-market, conservation of power and increases in reliability, will not be available to many important electronics market sectors.
Project Description: Purpose/Activities: 1) Development of EDA software to support the Control-element Assembly Tool (CAT) and revision of the Control-element Synthesis Tool (CST) to enhance their inter-operation. 2) Investigation of high-performance datapath structures for the joint demonstration project with Global Velocity on their GVS2000 product. In addition, through the universities (subawardees), work has begun on a delay based clock using a FLL (Frequency Locked Loop) for Blendics. It is a paper design along with simulations. It may be used in an improved synchronizer circuit which Blendics is currently developing. Work also includes creating and testing metastability simulation scrips as a part of development of MetaACE.
Jobs Summary: One FT Computer Hardware Engineer, One FT Computer Programmer, One PT Administrative Assistant, (Total jobs reported: 2)
Project Status: Less Than 50% Completed
This award's data was last updated on Aug. 31, 2009. Help expand these official descriptions using the wiki below.
Funds from this award have been disbursed to sub-grantees. Click here to see a list of sub-grantees.