The Pennsylvania State University
Grant: $480,000 - National Science Foundation - Sep. 1, 2009
No votes have been cast for this award yet
Join the conversation: Post a comment about this award
Award Description: The advent of multi-core architectures are expected to accentuate the already daunting memory- bandwidth problem. Supplying enough data to a single chip with a large number of on-die cores will become a major challenge for performance scalability. Three-dimensional integrated circuits (3D ICs) are envisioned as a promising solution to overcome the memory-wall barrier. In addition to high memory bandwidth, other benefits that 3D ICs can offer include the higher performance due to reduced average interconnect length, lower interconnect power consumption due to the reduction in total wiring length, and the support for the realization of mixed-technology heterogeneous chips. Intellectual Merit: Stacked 3D technology will benefit chip design in different ways: (1) Functional diversification using heterogenous integration to provide novel architectural features (e.g., customized acceleration layers, fast state recovery from power-down mode using stacked MRAMprocessor stacks) (2) Improved performance and power behavior from reduced interconnect length and improved bandwidth (3) Cost reduction from smaller chip footprint. The research will be conducted in collaboration with our industrial partners, including SRC companies IBM, Intel, Freescale, AMD, and others companies including Seagate, Synopsys, TSMC, as well as IMEC. Through close collaboration with several industry partners, especially SRC companies, we envision direct transfer of many ideas to industry. The outcome of this research will, therefore, have a direct impact on future multi-core designs.
Project Description: Towards achieving these potential benefits of 3D technology, this project involves two cross-cutting research thrusts related to architectural exploration and design-automation tools for 3D multi-core systems. As part of the architecture thrust, the stacking of memory components, including DRAM and non-volatile memory, and the relationship between memory stacking and interconnect will be explored. Further, we will identify new architectural features that can enable such integration. The stacking of customized logic layers that provide distinct service to the system such as improved reliability and efficient power management will also be investigated. We will consider the interplay between different constraints such as power delivery, thermal profiles, performance and cost in these explorations. To facilitate such explorations, a set of design automation toolsets will be developed. These include early-design analysis tools, cost and yield analysis tools, and the development of an OpenAccess 3D tool flow. In addition to validation using simulation and emulation environments, we will fabricate and test some of these designs to demonstrate the feasibility of our ideas. In this project we will recruit undergraduate students from the Honors College as well. We plan to develop a new undergraduate course that provides the students a spectrum of inter-related issues from technology to architectures. The tools and techniques developed in this research will be used in developing this new course. Finally, the tools will be made available through our web-sites for use by other educators, researchers, an industry practitioners. We will also organize tutorials along with major conferences to disseminate the results from this work.
Jobs Summary: Nothing to report currently. (Total jobs reported: 0)
Project Status: Not Started
This award's data was last updated on Sep. 1, 2009. Help expand these official descriptions using the wiki below.
No comments have been added for this project.